第三章习题参

3-1

由逻辑电路图可写出y的逻辑函数式： y=a(b+c)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY e3_1 IS

PORT (a,b,c: IN STD_LOGIC; y: OUT STD_LOGIC); END e3_1;

ARCHITECTURE behave OF e3_1 IS BEGIN

y<=a AND (b OR c); END behave;

3-2

(1) 行为描述方式 LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY e3_2 IS

PORT (a,b: IN STD_LOGIC; y: OUT STD_LOGIC); END e3_2;

ARCHITECTURE behave OF e3_2 IS BEGIN

y<=a XOR b; END behave;

(2) 数据流描述方式 LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY e3_2 IS

PORT (a,b: IN STD_LOGIC; y: OUT STD_LOGIC); END e3_2;

ARCHITECTURE dataflow OF e3_2 IS BEGIN

PROCESS(a,b)

VARIABLE x: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN x:=a &b; CASE x IS

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WHEN “00”=>y<=’0’; WHEN “01”=>y<=’1’; WHEN “10”=>y<=’1’; WHEN “11”=>y<=’0’; WHEN OTHERS=>y<=’Z’; END CASE; END PROCESS; END dataflow;

3-3

根据题中给定的真值表，编写程序如下： LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY e3_3 IS

PORT (s,r,d: IN STD_LOGIC; q,q_not: OUT STD_LOGIC); END e3_3;

ARCHITECTURE behav OF e3_3 IS BEGIN

PROCESS(clk) BEGIN IF(clk’EVENT AND clk=’1’) THEN IF (s=0 AND r=1) THEN q<=1; q_not<=0; ELSIF (s=1 AND r=0) THEN q<=0; q_not<=1; ELSE q<=d; q_not<=not d; END IF; END IF; END PROCESS; END behav;

3-4

VHDL源程序文件中注释的格式是：- -注释内容 即：在断续划线”- -”的后面写注释内容

3-5

设4选1数据选择器的通道输入信号为s1、s0，4个通道的数据输入分别为d0、d1、d2、d3，输出为f，编制程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; ENTITY e3_5 IS

PORT (s1,s0,d0,d1,d2,d3: IN STD_LOGIC;

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f: OUT STD_LOGIC); END e3_5;

ARCHITECTURE behav OF e3_5 IS BEGIN

PROCESS(s1,s0)

VARIABLE s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN s:=s1&s0; CASE s IS WHEN “00”=>f<=d0; WHEN “01”=>f<=d1; WHEN “10”=>f<=d2; WHEN “11”=>f<=d3; WHEN OTHERS=>f<=’Z’; END CASE; END PROCESS; END behav;

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